In the field of semiconductor device design, it is known that mechanical stresses within the device substrate can affect device performance. Stress engineering has come to play an important role in improving the performance of semiconductor devices. In the case of field-effect transistors (FETs), stress is applied to the channel region of the FET to cause increased mobility of electrons or holes, which in turn gives a substantial improvement in device speed. In a typical CMOS integrated circuit device, both n-type and p-type FETs (NFETs and PFETs respectively) are used. The stress components for the NFET and PFET in a given device must be engineered and applied differently, in accordance with the type of device and whether the direction is longitudinal (on the same axis as the channel current) or transverse to the channel current. It is known that the best stress design provides tensile stress in both longitudinal and transverse directions in the channel region under the gate of the NFET, but longitudinal compressive stress and transverse tensile stress in the channel region under the gate of the PFET.
FIGS. 1A and 1B schematically illustrate a typical device with the desired stress arrangement. FIG. 1A is a cross-section view of NFET and PFET gate structures 10, 20 formed on substrate 1 with an isolation region 15 (generally shallow-trench isolation or STI) between them. The NFET and PFET gate materials 11, 21 have channel regions 13, 23 beneath them. FIG. 1B is a plan view of the channel regions with the desired stresses, where arrows T and C represent tensile stress and compressive stress respectively.
U.S. Pat. No. 6,825,529 to Chidambarrao et al., assigned to one of the assignees of the present invention, describes the use of nitride spacers (12 and 22 in FIG. 1A) with different values of intrinsic stress to obtain the desired longitudinal stresses in the channel regions. According to Chidambarrao et al., it is also known that a nitride layer with high intrinsic stress, deposited over the completed NFET or PFET device, will induce corresponding stress in the channel.
The nitride films used in these techniques are deposited by plasma-enhanced CVD (PECVD). Whether a film has intrinsic tensile stress or compressive stress depends on the details of the deposition process. A number of PECVD processes and tools have been used in attempts to maximize intrinsic compressive stress in nitride films used in the PFET devices. At present the greatest compressive stress achievable in PECVD nitride appears to be about −2.6 GPa. There is a need for a process which can provide significantly greater intrinsic compressive stress in the deposited nitride film.